I didn't mean to link FP with LPAR - just to give an
example of what runs better on one processor than on
another. That's why there are FP units for PCs-the x86
can't do it as well. Sure, it can be written in
software, and is, but it's more efficient on hardware
made for the purpose. So there ARE differences in what
hardware can do - well.

There are clear differences in generations of 400
processors - n--way associativity of cache, how many
levels of cache, size, latency, I don't know what all.
And code, at the SLIC level, is compiled differently for
each variant. There are different instructions on the
various Intel chips, certainly it's no surprise that
there could be the same on the Power PC.

Sure, there's some marketing fufu, but not all, IMO.  :-)
> From: Tom Liotta <thomas@inorbit.com>
> You obviously missed the memo describing how these new processors have
> abandoned the use of binary bits for trinary "trits". By moving to the new
> trinary standard which registers positive, negative and neutral electric
> charge per "trit", entirely new features are possible.
>
> ===> One of the first machines I worked on used "decs", not
> puny "bits" or "trits". It seems that we are slowly working ourselves
> up to the level of 1960. Still have another factor 3.3333.. to go
> though.   :-)
>
> Seriously, none of this, not faster floating point Vern, are needed
> for fractional LPARs. But, as long as nobody will tell us the real
> truth behind this, this whole discussion is at best amusing.
> Where did I hear years ago, that "interactive feature" was
> hardware? even came on or needed a special "decelerator"
> hardware card...  :-)
>
>
>
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